The present invention relates generally to low power audio DAC systems, for example, audio DAC systems adapted to be used in portable audio systems to play back digital audio data in analog format (for example by decoding it from compressed MP3 format or by receiving it in PCM (pulse code modulation) format supplied by a digital signal processor), while minimizing power consumption. The invention also relates more particularly to such audio DAC systems which include a sample rate converter in an audio digital to analog converter (“audio DAC”) wherein the audio DAC is not required to be locked in synchronization with the sampling rate of the audio input data.
Audio digital to analog converters (DAC) are widely used in various applications, such as cell phones and MP3 players, wherein the digital audio samples are played back by means of speakers and/or headphones. Because audio signals are increasingly stored and processed in digital format, the number of applications of audio DACs are increasing.
Normally, a digital signal processor performs a decoding if the original audio data are compressed, and then processes and transfers the decoded and processed audio data to the audio DAC continuously at the audio data sampling rate. The audio DAC receives the audio data and plays it at a rate derived from the externally provided operating clock rate. Typically, the operating clock rate is 512, 256 or 128 times the audio sampling rate. The DSP (digital signal processor) can operate very fast, so it does not have to run continuously to accomplish the required decoding and processing tasks. Unfortunately, the continuous audio data transfer from the DSP to the audio DACs of the prior art requires that the DSP remain in a “powered up” mode even though there are not any other actions presently required to be performed by the DSP. Under these conditions, circuitry and associated software not related to the audio data transfer from the DSP continue to consume and therefore waste power.
An audio DAC ordinarily consists of two parts, including a digital processing circuit which interpolates (and sometimes performs other processing on) the incoming audio data. The interpolated data may be processed by a digital delta-sigma modulator, the output of which typically is provided as an input to an analog DAC. In conventional audio DACs, the audio data is interpolated by multi-stage interpolation filters and then is fed into a digital delta-sigma modulator. The digital delta-sigma modulator is used to reduce the audio data word width and push quantization noise out of the audio band to reduce distortion caused by nonlinearity of an analog DAC section of the audio DAC. The reduced width audio data words are converted into analog signals by the analog DAC.
Various analog audio sources often are sampled at various different sample frequencies and the sampled signals then are digitized to produce various audio signals which can be readily edited, reproduced and processed easily in digital format without introducing nearly as much distortion and noise as would be introduced if the same editing, reproducing and processing were to be performed on the same audio signals in analog format.
Ordinarily, audio DACs operate at clock signal rates that are locked in synchronization with the digital audio input sampling rates, in order to avoid pitch shift artifacts. The effect of the pitch shift artifacts is that the tone at the analog output is not exactly at the frequency it is supposed to be. For example, if the DAC is operating at 48.5 kHz while playing a 1 kHz tone recorded at 48 kHz, the tone at the DAC output will be 1.01 kHz instead of 1 kHz. There are several typical sampling rates for digital audio data, so clock signals related to those typical sampling rates need to be available for clocking the audio DAC to enable it to “play back” the received digital audio at different audio sampling rates. To achieve high quality audio output, the clock signals being utilized need to have low jitter. The jitter of the DAC clock has an FM modulation effect on the audio signals. For example, if the jitter is sinusoidal and the playback audio signal is a tone, there will be two “side tones” at each side of the main audio tone, and the distance of each side tone to the main audio tone is equal to the jitter frequency. In some applications, it is difficult to provide analog DAC clock signals that meet the foregoing requirements. That is, a low jitter clock signal which has a frequency related to the audio sampling rate is not conveniently available in some applications.
Normally, in the prior art a clock signal having a frequency that is directly related to the sampling rate is needed. Otherwise, a PLL (phase locked loop) must be used to generate a sampling-rate-related clock signal from a clock signal that is not directly related to the sampling rate. However, it would be highly desirable for some audio DAC applications that any reference signal, such as the output of a free-running oscillator, could be used for controlling the operating rate of the analog DAC section of an audio DAC.
Sample rate converters are necessary for interfacing between devices receiving and/or producing digital signals having different sample rates, in order to avoid audio sample dropping or sample repeating which results in highly undesirable audible “popping” or “clicking” sounds. Even for two devices that receive and/or produce digital signals having the same nominal sample rates but which are based on two asynchronous clocks, it is necessary to use an asynchronous sample rate converter to accomplish interfacing between the two devices in order to avoid audio sample dropping or repeating.
In asynchronous sample rate converters it is not necessary that the sample rate of the output signal be synchronized with the sample rate of the input signal. Asynchronous sample rate converters each receive a stream of input samples, process them, and produce output samples when requested, and can be used to convert between any two sample rates irrespective of whether the ratio of the two sample rates is an integer or is a rational number, and irrespective of whether the two sample rates are synchronized.
Because of this feature, an asynchronous sample rate converter can decouple a first digital audio device producing a digital output having a first sample rate from a second digital audio device which is intended to receive the output of the first digital audio device and sample it at a second sample rate. For example, the sample rate of an audio source device might be 48 kHz, and the desired sample rate for an audio destination device might also be 48 kHz, but the clock signals of the audio source device and the audio destination device might be independent and therefore asynchronous. In this case, even though the nominal sample rates both are 48 kHz, a very small drift or difference between the frequencies of the two above-mentioned 48 kHz clock signals will accumulate and cause the above-mentioned undesirable/annoying sample dropping or sample repeating if a synchronous sample rate converter is used.
One asynchronous sample rate converter is disclosed in the assignee's co-pending patent application “ASYNCHRONOUS SAMPLE RATE CONVERTER AND METHOD” Ser. No. 10/325,202, filed Dec. 20, 2002 by Xianggang Yu, Terry L. Sculley and Jung-Kuei Chang, Published Jun. 24, 2004 as Publication No. US 2004/0120361 A1.
There is an unmet need for a way to reduce power consumption of a system including an audio DAC system and a host processor such as a DSP.
There also is an unmet need for a way to avoid the need to continuously maintain a DSP of a system including an audio DAC system and the DSP in a powered up mode.
There also is an unmet need for a way to provide improved flexibility in the transfer of audio data from a DSP to an audio DAC system.